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2014-12-11dts: ls1021a: add the RCPM node and change FPGA's compatibleChenhui Zhao
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ib0ecd4424f3d356fe1bcd687d3befd61527be5ab Reviewed-on: http://git.am.freescale.net:8181/21974 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021aqds: reduce the frequency for dspi flashChao Fu
Dspi flash is at45db021d on ls1021aqds board. Reduce its frequency to improve the data transfer stability. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: If4e4d03d52fc28dea2dca3e6c6872024d3d1229a Reviewed-on: http://git.am.freescale.net:8181/21973 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11esdhc: defconfig: Add LS1021A SD support.Qiu Wujie
Signed-off-by: Qiu Wujie <B49553@freescale.com> Change-Id: I30e6c4e9c5f6859aecc586b21d6426a802160699 Reviewed-on: http://git.am.freescale.net:8181/21964 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: pm: add deep sleep support for LS1Chenhui Zhao
LS1 supports deep sleep feature that can switch off most parts of the SoC when it is in deep sleep state. The DDR controller will also be powered off in deep sleep. Therefore, copy the last stage code to enter deep sleep to SRAM and run it with disabling MMU and caches. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> --- Patch Sent Upstream url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296411.html Change-Id: If96ace364c21786cc88ea4979d7cbb4e177da0a2 Reviewed-on: http://git.am.freescale.net:8181/21920 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM:LS1021aQDS: add CPU hotplug platform supportZhang Zhuoyu
This is only a CPU pseudo-hotplug, and incompatible with kexec mechanics. As per the discussion with Russell King in opensource community, CPU hotplug should reset the secondary core to be compatible with kexec. "In the kexec case, when the secondary CPU wakeup, the code it is executing can already been overwritten, which then means that the CPU ends up executing some random code instead." For LS102x platforms, resetting core can be realized, but come across cache coherence problem which is still unresolved, we will submit another patch to implement CPU hotplug by resetting core once cache coherence issue resloved. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> --- Patch Sent Upstream url: https://lkml.org/lkml/2014/9/26/422 Change-Id: I36509f99299f874ef0df891a33c907a749649527 Reviewed-on: http://git.am.freescale.net:8181/21918 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling codeNicolas Pitre
This code is becoming duplicated in many places. So let's consolidate it into a handy macro that is known to be right and available for reuse. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from 39792c7cf3111d69dc4aa0923859d8b929e9039f Change-Id: I9e2e9715425bcb8493c32b46ecb41c568d8235c5 Reviewed-on: http://git.am.freescale.net:8181/21917 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 7885/1: Save/Restore 64-bit TTBR registers on LPAE suspend/resumeMahesh Sivasubramanian
LPAE enabled kernels use the 64-bit version of TTBR0 and TTBR1 registers. If we're running an LPAE kernel, fill the upper half of TTBR0 with 0 because we're setting it to the idmap here (the idmap is guaranteed to be < 4Gb) and fully restore TTBR1 instead of just restoring the lower 32 bits. Failure to do so can cause failures on resume from suspend when these registers are only half restored. Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8 Change-Id: I7e91a04ac2fda61f9c8a5e60d8d503d00a3cf9c1 Reviewed-on: http://git.am.freescale.net:8181/21910 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 8053/1: kernel: sleep: restore HYP mode configuration in cpu_resumeLorenzo Pieralisi
On CPUs with virtualization extensions the kernel installs HYP mode configuration on both primary and secondary cpus upon cold boot. On platforms where CPUs are shutdown in idle paths (ie CPU core gating), when a CPU resumes from low-power states it currently does not execute code that reinstalls the HYP configuration, which means that the kernel cannot run eg KVM properly on such machines. This patch, mirroring cold-boot behaviour, executes position independent code that reinstalls HYP configuration and drops to SVC mode safely on warmboot, so that deep idle states can be enabled in kernel running as hosts on platforms with power management HW. Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Dave Martin <dave.martin@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from 0e0779da2233f2dfc85e9c3a6ea142476d326811 Change-Id: Iafed877cc49e799d7c31f1cb265a0b38be708c88 Reviewed-on: http://git.am.freescale.net:8181/21909 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dtsi:ls1021a:Add the DSPI transfer mode property in DSPI nodeChao Fu
DSPI new driver can select transfer mode(tcfq/eoq) to work. The property will be read from dtsi node. Add the property tcfq-mode for LS1021a. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: Ib659338777a4a8a5fdef7914c556c3ca8b4c483d Reviewed-on: http://git.am.freescale.net:8181/21908 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11audio: dts: Add dts nodes on LS1021AQDS/TWRAlison Wang
This patch adds dts nodes for audio support on LS1021AQDS/TWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Change-Id: I5e98a2377a7230598401ad932c4016951435b240 Reviewed-on: http://git.am.freescale.net:8181/21061 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dts: ls1021a: updated the soc nodeTang Yuantian
Added device_type property to soc node to facilitate its use. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I4c50770215608f8ca718e78072a28f69afdf1bc2 Reviewed-on: http://git.am.freescale.net:8181/21690 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dts: ls1021a: updated the clockgen nodeTang Yuantian
Fixed some error in clockgen node. This patch also added clock source to CPU nodes to support CPU frequency switch dynamically. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I2d40c3bc9c766d62d9cb8a3c00b9d5e1c2e65f41 Reviewed-on: http://git.am.freescale.net:8181/21689 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021aqds: add qe node to ls1021aqds dtsZhao Qiang
add qe node(qe-tdm and qe-uart) into ls1021a-qds.dts Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I1ab52c2330246e807fd4c96103d2c063b6d8d8ba Reviewed-on: http://git.am.freescale.net:8181/21868 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a/dts: Add device nodes for FlexCAN IP instancesBhupesh Sharma
This patch adds the device nodes for 4 FlexCAN IP instances available on LS1021A SoC in the ls1021a.dtsi file and enables only the first two instances which are supported on the QDS board in ls1021a-qds.dts file. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- Previous version of this patch under review upstream: http://patchwork.ozlabs.org/patch/363588/ Will re-spin the patch with the DTS Change-Id: I592e5f8562ad173801a53433aec9a91b00ba8bb0 Reviewed-on: http://git.am.freescale.net:8181/21855 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11Enable IFC for ls1021Jaiprakash Singh
Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Change-Id: I501144de5deaecb1bbbe913fc1ef82e8102d84a3 Reviewed-on: http://git.am.freescale.net:8181/21811 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm/dts/ls1021a: Add GPIO controller nodesShaveta Leekha
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Change-Id: Ib16b8e2466757d782ec4bb5e8549f2dcb9208e32 Reviewed-on: http://git.am.freescale.net:8181/21801 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11gpio: enable GPIO support in ls1021a_defconfigShaveta Leekha
LS1021a-qds has the same controller as GPIO on powerpc platform(MPC8XXX), so remove GPIO_MXC and add the one for GPIO_MPC8XXX Enable gpio as default Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Change-Id: I13531087c312ef9fa3bb607b5202592d13b29727 Reviewed-on: http://git.am.freescale.net:8181/21800 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a-twr:correct qspi flash informationChao Fu
Correct qspi flash information on ls1021a-qds board. And remove flash partion in node, it is not useful. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: I8b2dc47446c5d54ce12e3d7d138fa9d9a3b9ba6c Reviewed-on: http://git.am.freescale.net:8181/21364 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a-qds:correct qspi flash informationChao Fu
Correct qspi flash information on ls1021a-qds board. And remove flash partion in node, it is not useful. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: Ib9b3964127984457032f73be53bbfc847cf438bf Reviewed-on: http://git.am.freescale.net:8181/21360 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a:add qspi-memory address and correct qspi compatibleChao Fu
The new QSPI driver add DDR read mode, so add qspi-memory map for QSPI access in DDR mode in dts node. Modify qspi node compatible for LS1 paltform. Signed-off-by: Chao Fu <b44548@freescale.com> Change-Id: Ia92dda63bf857b845767ae62f2c7eb9a84371aa1 Reviewed-on: http://git.am.freescale.net:8181/21356 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a: Enable GIANFAR for LS1Claudiu Manoil
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: Ie34306997587de53d71a44d643989a3808644a4c Reviewed-on: http://git.am.freescale.net:8181/21178 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: ls1021a: add gating clocks to IP blocks.Xiubo Li
A given application may not use all the peripherals on the device. In this case, it may be desirable to disable unused peripherals. DCFG provides a mechanism for gating clocks to IP blocks that are not used when running an application. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- This patch has been sent out to the community and under discussion： URL：http://www.spinics.net/lists/arm-kernel/msg370133.html Change-Id: Iedf07d12955b3fa011a0bef27236f73405cefb44 Reviewed-on: http://git.am.freescale.net:8181/21604 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11fb: dcu: convert to use regmap API.Xiubo Li
The regmap framework has one feature of register cache, which will be more easy to add big endian mode and PM support. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> -- The first DRM version will be send out to the community before 15 Dec 2014. Change-Id: I3aa3c30f4ab42b64b80669b483b45a62ae31d6bb Reviewed-on: http://git.am.freescale.net:8181/21571 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a-twr: add SII9022A HDMI DT nodeXiubo Li
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- The first DRM version will be send out to the community before 30 November 2014. Change-Id: Ia5538da4db87431fd80ffaacc07c201d20a8bc2b Reviewed-on: http://git.am.freescale.net:8181/19651 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: dts: ls1021a: Add DCU nodeXiubo Li
This patch adds DCU node in SoC level DTS for Freescale LS1021A-TWR. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- The first DRM version will be send out to the community before 30 November 2014. Change-Id: I74671a92d530699be6868f7f1591eadbd40a6879 Reviewed-on: http://git.am.freescale.net:8181/19649 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dtsi: ls1021a: Add 40-bit dt node support for DCU.Xiubo Li
Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- The first DRM version will be send out to the community before 30 November 2014. Change-Id: I6a20f9f5c1b8b8c596e635b25aa37055e23f82a7 Reviewed-on: http://git.am.freescale.net:8181/19648 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a-twr/qe: add qe node to ls1-twrZhao Qiang
add qe node to ls1021atwr fdt. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- upstream link: http://patchwork.ozlabs.org/patch/398470/ it is under discussion. Change-Id: I4f0bc40003265f85bde01a9982ef7f91edd1d08e Reviewed-on: http://git.am.freescale.net:8181/21121 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11qe-uart: modify qe-uart to adapt both powerpc and armZhao Qiang
qe has been supported by arm board ls1021, qe-uart need to be supported by ls1021. modify the code to make qe-uart can work on both powerpc and ls1021. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- upstream link: http://patchwork.ozlabs.org/patch/398471/ it is under discussion. Change-Id: I07a9a091882cd572330b38e7a6e0632aea9a9042 Reviewed-on: http://git.am.freescale.net:8181/21119 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11Revert "arm: ls1021a: remove the FSL_SOC config added by SOC_LS1021A"Jingchang Lu
This reverts commit 14bbc976701a2ebc62343d3122e5ff772060a35f. LS1021A shares IPs with sophisticated PowerPC platform, many PowerPC drivers have depends on FSL_SOC defination, so to consistent with this, FSL_SOC is introduced. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: Ie5a69b78d317d09f9fee54dde3f1cd4bffdb9588 Reviewed-on: http://git.am.freescale.net:8181/19915 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a: add PCIe device nodeMinghuan Lian
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I5deb88a99bd7b5d40251a4935d4d8a556abad7ae Reviewed-on: http://git.am.freescale.net:8181/19712 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1021a: remove dma_zone_size definationJingchang Lu
CONFIG_ZONE_DMA is enough to claim the dma limitation, and no need for limitation smaller than 4GB, so remove the dma_zone_size defination. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- the upstream include this change in patchwork is: https://patchwork.kernel.org/patch/4946151/ Change-Id: Ia2ed1fd18519e1e2553e2aa8ce1c1729657a6ed3 Reviewed-on: http://git.am.freescale.net:8181/19874 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: configs: ls1021a: enable LTC2945, WDT and CLK_QOIRQJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I7cde95ba1ca9acbf6d2d01649b3ecb3d08db02c1 Reviewed-on: http://git.am.freescale.net:8181/19912 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Hongtao Jia <hongtao.jia@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11Add LTC2945 node to ls1021a-twr.dtsJia Hongtao
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Change-Id: I08008c3dcd2b85b0c54b9f9ee939287f57745517 Reviewed-on: http://git.am.freescale.net:8181/19641 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: add wakeup device ftm0 node for ls1021aWang Dongsheng
Add ftm0 node, cause of ftm0 can be set as a alarm before system going to deep sleep. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: Ie337ec554f6acd625cd691a0e07ffb96807cfa10 Reviewed-on: http://git.am.freescale.net:8181/19838 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm : dts : ls1021a : Modify USB3.0 dts nodeSuresh Gupta
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: I7aa37e4914623a303eb520c6d8fd6d4f84e9ddb2 Reviewed-on: http://git.am.freescale.net:8181/19815 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm : dts : ls1021a : Remove unwanted code from USB2.0 dts nodeNikhil Badola
Remove #address-cells and #size-cells from USB 2.0 node in ls1021a Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: Ia2ff9aea201ef18b352437bda267571c235db689 Reviewed-on: http://git.am.freescale.net:8181/15675 Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: add alias for the clockgen sysclk nodeJingchang Lu
This add an alias named sysclk for the sysclk node for fdt fixup procedure locating it uniquely. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I7e6bd6cb4d81fe44c73944be91cab3fe56810094 Reviewed-on: http://git.am.freescale.net:8181/19199 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: change sysclk compatible to "fixed-clock"Jingchang Lu
The sysclk could be well probed by "fixed-clock" compatible, no custom compatible is needed any more. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I17a21e20ced4304e716e5a9ba07ff56b2adb45a7 Reviewed-on: http://git.am.freescale.net:8181/17833 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: remove the tbi node from SoC level dtsJingchang Lu
remove the tbi node which will be added to boards level dts. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I1b7893526e63d0207637f2ae0576c9d5f62a6a06 Reviewed-on: http://git.am.freescale.net:8181/17829 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a-twr: add aliases for enet phyJingchang Lu
This add aliases for enet phy to make it be found easily in u-boot on dynamically change the enet "phy-handle" and "phy-connection-type" property. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I60e19aa48856c9b9048415d1c8924b626d70332a Reviewed-on: http://git.am.freescale.net:8181/17831 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a-qds: add tbi node and aliases for enet phyJingchang Lu
This move the tbi node to boards level device tree source. And add aliases for enet phy to make it be found easily by u-boot on dynamically change the enet "phy-handle" and "phy-connection-type" property. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I80748fdbbeab06cb5804128600369317dbececd6 Reviewed-on: http://git.am.freescale.net:8181/17830 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1021a: remove the FSL_SOC config added by SOC_LS1021AJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I2deac22e04a04c2523c7839d5974a41288e5bb2b Reviewed-on: http://git.am.freescale.net:8181/17837 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: change duart compatible to "fsl,16550-FIFO64"Jingchang Lu
this patch change the duart compatible to 64-byte FIFO mode. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I4d306671daed4262a6f354a3507304d82468c41d Reviewed-on: http://git.am.freescale.net:8181/17835 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: configs: add Freescale LS1021A initial defconfigJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: Ia3ba1dbeb66d4c929cfe19122d221a2af36377f8 Reviewed-on: http://git.am.freescale.net:8181/17838 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: imx: Add Freescale LS1021A SMP supportJingchang Lu
Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464481/
2014-12-11ARM: imx: Add initial support for Freescale LS1021AJingchang Lu
The LS1021A SoC is a dual-core Cortex-A7 based processor, this add the initial support for it. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464451/
2014-12-11ARM: dts: Add initial LS1021A TWR board dts supportJingchang Lu
Signed-off-by: Chen Lu <B46807@freescale.com> Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464461/
2014-12-11ARM: dts: Add initial LS1021A QDS board dts supportJingchang Lu
Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464471/
2014-12-11ARM: dts: Add SoC level device tree support for LS1021AJingchang Lu
Add Freescale LS1021A SoC device tree support Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Adrian Sendroiu <adrian.sendroiu@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464491/
2014-12-11ARM: call of_clk_init from default time_init handlerSebastian Hesselbarth
Most DT ARM machs require common clock providers initialized before timers. Currently, arch/arm machs use .init_time to call of_clk_init right before clocksource_of_init. This prevents to remove that callback and use the default one instead. This patch adds a call to of_clk_init() to the default .init_time callback for COMMON_CLK enabled machs to allow to remove custom callbacks where applicable. While at it, also reorder includes alphabetically. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- This patch is pulled back from upstream: commit 4178bac4f6e955869395b30246687d41183a5edb
generated by cgit v0.10.2 at 2024-07-13 02:49:58 (GMT)