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path: root/drivers/clk/zynq/pll.c
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2013-08-20clk/zynq/pll: Use #defines for fbdiv min/max valuesSoren Brinkmann
Use more descriptive #defines for the minimum and maximum PLL feedback divider. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-08-20clk/zynq/pll: Fix documentation for PLL register functionSoren Brinkmann
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-05-21clk: zynq: Factor out PLL driverSoren Brinkmann
Refactor the PLL driver so it works with the clock controller driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Mike Turquette <mturquette@linaro.org>