Age | Commit message (Collapse) | Author |
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Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
arch/arm/kvm/mmu.c
arch/arm/mm/proc-v7-3level.S
arch/powerpc/kernel/vdso32/getcpu.S
drivers/crypto/caam/error.c
drivers/crypto/caam/sg_sw_sec4.h
drivers/usb/host/ehci-fsl.c
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There are (probably rare) situations when a system crashed and the system
console becomes unresponsive but the network icmp layer still is alive.
Wouldn't it be wonderful, if we then could submit a sysreq command via ping?
This patch provides this facility. Please consult the updated documentation
Documentation/sysrq.txt for details.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
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Jon Masters developed this wonderful SMI detector. For details please
consult Documentation/hwlat_detector.txt. It could be ported to Linux
3.0 RT without any major change.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
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This patch provides a recording mechanism to store data of potential
sources of system latencies. The recordings separately determine the
latency caused by a delayed timer expiration, by a delayed wakeup of the
related user space program and by the sum of both. The histograms can be
enabled and reset individually. The data are accessible via the debug
filesystem. For details please consult Documentation/trace/histograms.txt.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Currently, pcie-designware.c only supports two ATUs, ATU0 is used
for CFG0 and MEM, ATU1 is used for CFG1 and IO. There is a conflict
when MEM and CFG0 are accessed simultaneously. The patch adds
'num-atus' property to PCIe dts node to describe the number of
PCIe controller's ATUs. If num_atus is bigger than or equal to 4,
we will change ATUs assignment: ATU0 for CFG0, ATU1 for CFG1,
ATU2 for MEM, ATU3 for IO.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
The patch is upstreaming
http://patchwork.ozlabs.org/patch/409170/
Change-Id: I317bf8a3648eafeb221da6479b7788de0028d8c5
Reviewed-on: http://git.am.freescale.net:8181/23496
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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To implement CPU=Host we have added KVM_ARM_PREFERRED_TARGET
vm ioctl which provides information to user space required for
creating VCPU matching underlying Host.
This patch adds info related to this new KVM_ARM_PREFERRED_TARGET
vm ioctl in the KVM API documentation.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 740edfc0a35dd688c97ae8907c4377df49219bf3)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I8f296cf1489e3095211137182ff457285671da8e
Reviewed-on: http://git.am.freescale.net:8181/22040
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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A given application may not use all the peripherals on the device.
In this case, it may be desirable to disable unused peripherals.
DCFG provides a mechanism for gating clocks to IP blocks that are
not used when running an application.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
This patch has been sent out to the community and under discussion:
URL:http://www.spinics.net/lists/arm-kernel/msg370133.html
Change-Id: Iedf07d12955b3fa011a0bef27236f73405cefb44
Reviewed-on: http://git.am.freescale.net:8181/21604
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Revert this to prepare for pulling many other open source patches.
This reverts commit 74b86665568cc09a0a2ba37dba11ec7f71295424.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Change-Id: Icd4b64a9e263b9aee317efe626d3853865fccf71
Reviewed-on: http://git.am.freescale.net:8181/21404
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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IFC registers can be of type Little Endian
or big Endian depending upon Freescale SoC.
Here SoC defines the register type of
IFC IP.So update accessors functions with
common IFC accessors functions to take
care both type of endianness.
IFC IO accressor are set at run time based
on IFC IP registers endianness.IFC node in
DTS file contains information about
endianness.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
---
This patch is under reviewing at url - https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg741449.html
Change-Id: Ib6d4669a94afa50e71ce522a008232fa21b0bc19
Reviewed-on: http://git.am.freescale.net:8181/20971
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Freescale IFC controller has been used for mpc8xxx.
It will be used for ARM-based SoC as well. This patch
moves the driver to driver/memory and fix the header
file includes.
Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall()
to make sure this module has been loaded before
MTD partition parsing starts.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Cherry-picked from:d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc
Change-Id: I3cc83c716adf27a4988b818d57706980dbbefdea
Reviewed-on: http://git.am.freescale.net:8181/20970
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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Signed-off-by: Jason Chen <b02280@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
The maintainer or many other people all have strong opinions to
add HDMI driver based the DRM framework.
The mails URL:
https://lkml.org/lkml/2014/9/5/37
The first DRM version of HDMI will be send out to the community
before 30 November 2014.
Change-Id: I2cce28cb70dd0be6e8bc09c2ab7f5cabbe98dbdf
Reviewed-on: http://git.am.freescale.net:8181/19650
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The Display Controller Unit (DCU) module is a system master that
fetches graphics stored in internal or external memory and displays
them on a TFT LCD panel. A wide range of panel sizes is supported
and the timing of the interface signals is highly configurable.
Graphics are read directly from memory and then blended in real-time,
which allows for dynamic content creation with minimal CPU intervention.
The features:
(1) Full RGB888 output to TFT LCD panel.
(2) For the current LCD panel, WQVGA "480x272" is supported.
(3) Blending of each pixel using up to 4 source layers dependent on
size of panel.
(4) Each graphic layer can be placed with one pixel resolution in
either axis.
(5) Each graphic layer support RGB565 and RGB888 direct colors without
alpha channel and BGRA8888 direct colors with an alpha channel.
(6) Each graphic layer support alpha blending with 8-bit resolution.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
The maintainer and many other people all have strong opinions to
add DCU driver based the DRM framework.
The mails URL:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-September/197863.html
The first DRM version of DCU will be send out to the community
before 30 November 2014.
Change-Id: I9feb7c9b975431a1bb3906eb955dcf6ae09654eb
Reviewed-on: http://git.am.freescale.net:8181/19647
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chao Fu <B44548@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Chao Fu <b44548@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit c99428d035908b9c0b8be452f9b091bc5e090256)
Change-Id: I4afafcd1d5fd244ea287f899bca03baa95c61531
Reviewed-on: http://git.am.freescale.net:8181/20091
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Freescale DSPI module will have two endianess in different platform,
but ARM is little endian. So when DSPI in big endian, core in little endian,
readl and writel can not adjust R/W register in this condition.
This patch will remove general readl/writel, and import regmap mechanism.
Data endian will be transfered in regmap APIs.
Documents: dspi add bool "big-endian" in dts node if DSPI module
work in big endian.
Signed-off-by: Chao Fu <b44548@freescale.com>
Reviewed-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 1acbdeb92c87fc18eade0815dedc257fe45b88b7)
Change-Id: I60e630bb18a2101af3154633bbe5824a52ac45f2
Reviewed-on: http://git.am.freescale.net:8181/20086
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The patch updates the document by adding more information to describe the
DT proporties used by the Freescale Quadspi driver and the childs nodes.
For the child node for SPI NOR flash, we add the required property
("spi-max-frequency"), and refer to spi-nor-flash.txt for the optional
properties.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch: http://patchwork.ozlabs.org/patch/343229/
Change-Id: Ib625035f0fd863840eca9dce66699836883bdfe3
Reviewed-on: http://git.am.freescale.net:8181/20128
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds the binding file for Freescale QuadSPI driver.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
(cherry picked from commit c7a8a11c6bb78f49895d42294a88002ea544922f)
Change-Id: I1af8259f5518ae733eae21f9f21ca13b827adba3
Reviewed-on: http://git.am.freescale.net:8181/20127
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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We need a DT property to store the dummy cycles for DDR Quad read.
This is a common feature for the SPI NOR flash, such as Spansion and Micron
chips.
Add this file to describe this specific SPI NOR flash features which will
be referred by the SPI NOR flash drivers.
Signed-off-by: Huang Shijie <b32955@freescale.com>
This patch was under discussion at: https://patchwork.kernel.org/patch/4074941/
Change-Id: Id5eac26d6ee941a0976721a704881bc7012716ad
Reviewed-on: http://git.am.freescale.net:8181/20126
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add support for Freescale Layerscape PCIe controller. This driver
re-uses the designware core code.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I799aa1cd488a44b4ba9c198694f75d56b2294a03
Reviewed-on: http://git.am.freescale.net:8181/19711
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Device-Tree binding for device endianness
Index Device Endianness properties
---------------------------------------------------
1 BE 'big-endian'
2 LE 'little-endian'
For one device driver, which will run in different scenarios above
on different SoCs using the devicetree, we need one way to simplify
this.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
---
This patch is pulled back from upstream:
commit 275876e208e28abf4b96ec89030e482b1331ee75
Change-Id: I28bbebb0b8e191555b7a7b001d9f4d04453a3106
Reviewed-on: http://git.am.freescale.net:8181/19856
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The same FTM PWM device can have a different endianness on different
SoCs. The device tree provides a property to describing this so that an
operating system device driver can handle all variants of the device.
Refer to the table below for the endianness of the FTM PWM block as
integrated into the existing SoCs:
SoC | FTM-PWM endianness
--------+-------------------
Vybrid | LE
LS1 | BE
LS2 | LE
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit a535e2e0debc2255fcf60a11d73fbb0534454cc3
Change-Id: Icf9f1efe7a4fd121cb5568f8552c01043110b108
Reviewed-on: http://git.am.freescale.net:8181/19867
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This adds the binding documentation for Freescale FlexTimer Module
(FTM) PWM driver under Documentation/devicetree/bindings/pwm/.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Yuan Yao <yao.yuan@freescale.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit 42586315b7b6e682bd4136a1a2bc2b1d50113487
Change-Id: I5bf1419bcfbb4bd84c6e3eb2285fad660835fda3
Reviewed-on: http://git.am.freescale.net:8181/19863
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The FTM binding could be used on Vybrid and LS1+, add a binding
document for it.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
This patch is pulled back from upstream:
commit 12e499d0ed1fa09940a573e5a8cce52b556f3c38
Change-Id: I7e3a87401852f29e83768a44b49dc261a4d67b28
Reviewed-on: http://git.am.freescale.net:8181/19861
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This watchdog driver will be working on IMX2+, Vybrid, LS1, LS2+
platforms, and will be in different endianness mode in those SoCs:
SoCs WDT endian mode
------------------------------------
IMX2+ LE
Vybird LE
LS1 BE
LS2 LE
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
---
This patch is pulled back from upstream:
commit f728f4bfc495a588abda4661c09595112677be25
Change-Id: I679a13328e7ee02fbc23dad99a3e672c6186fc4c
Reviewed-on: http://git.am.freescale.net:8181/19717
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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LTC2945 is a system monitor that measures current, voltage, and power.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
(cherry picked from commit 6700ce035f830149d48c270d84736debfb67179e)
Change-Id: I7d658c4e03f5e9108fbf1e407b3f1bdecda7ef1d
Reviewed-on: http://git.am.freescale.net:8181/19634
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I667cb31ce4b5e8f5c2a4c5f2b88e677eb991b9b3
Reviewed-on: http://git.am.freescale.net:8181/17834
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add Freescale enhanced direct memory(eDMA) controller support.
This module can be found on Vybrid and LS-1 SoCs.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
---
This patch is pulled back from upstream:
commit d6be34fbd39b7d577d25cb4edec538e8990ba07c
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use exact SoC revision instead of wildcard describing
to make the binding more clearer.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
---
This patch has been sent to upstream:
https://patchwork.kernel.org/patch/4544291/
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Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
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Change-Id: I1e757f85419d66bfca4bbf6d4097a871c3b68bc8
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/16878
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Tested-by: Mandy Lavi <Mandy.Lavi@freescale.com>
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There are (probably rare) situations when a system crashed and the system
console becomes unresponsive but the network icmp layer still is alive.
Wouldn't it be wonderful, if we then could submit a sysreq command via ping?
This patch provides this facility. Please consult the updated documentation
Documentation/sysrq.txt for details.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
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Jon Masters developed this wonderful SMI detector. For details please
consult Documentation/hwlat_detector.txt. It could be ported to Linux
3.0 RT without any major change.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
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This patch provides a recording mechanism to store data of potential
sources of system latencies. The recordings separately determine the
latency caused by a delayed timer expiration, by a delayed wakeup of the
related user space program and by the sum of both. The histograms can be
enabled and reset individually. The data are accessible via the debug
filesystem. For details please consult Documentation/trace/histograms.txt.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
arch/sparc/Kconfig
drivers/tty/tty_buffer.c
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commit 1b31e9b76ef8c62291e698dfdb973499986a7f68 upstream.
Add Device ID of Intel BayTrail SMBus Controller.
Signed-off-by: Chew, Kean ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
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This reverts commit cf42c0223c36e5fc2bc99ac01a7dec2ba5ccfec6.
This patch is a old methods, and platform operation shouldn't in
driver code. The patch has been replaced by the new patch. And for
binding also not need to modify.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: I5abf5c05400082b18822bcdd03117b7698ec859c
Reviewed-on: http://git.am.freescale.net:8181/11644
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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master-tmp is the master branch as of
8b60f5ea90c49344692a70f62cd4aa349de38b48
with the following commits reverted due to excessive conflicts:
commit b35a69559c46e066e6f24bb02d5a6090483786e3
Author: Scott Wood <scottwood@freescale.com>
Date: Fri Apr 18 15:27:52 2014 -0500
Revert "net: add sysfs helpers for netdev_adjacent logic"
This reverts commit 0be682ca768d671c91cfd1379759efcb3b29102a.
commit 1c0dc06e47e11bf758f3e84ea90c2178a31dbf0f
Author: Scott Wood <scottwood@freescale.com>
Date: Fri Apr 18 15:27:47 2014 -0500
Revert "net: rename sysfs symlinks on device name change"
This reverts commit 45ce45c69750b93b8262aa66792185bd49150293.
Conflicts:
drivers/iommu/fsl_pamu.c
drivers/net/bonding/bond_3ad.c
drivers/net/bonding/bond_sysfs.c
drivers/net/bonding/bonding.h
drivers/net/ethernet/freescale/gianfar.c
Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
drivers/iommu/fsl_pamu.c
drivers/net/bonding/bond_3ad.c
drivers/net/bonding/bond_sysfs.c
drivers/net/bonding/bonding.h
drivers/net/ethernet/freescale/gianfar.c
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[ Upstream commit ebf4ad955d3e26d4d2a33709624fc7b5b9d3b969 ]
Few platforms use external regulator to keep the ethernet MAC supplied.
So, request and enable the regulator for driver functionality.
Fixes: 66fda75f47dc (regulator: core: Replace direct ops->disable usage)
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Suggested-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
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Added port indexes and compatible strings for each port
and for the L2 switch node itself.
Added L2 switch device tree binding.
Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com>
Change-Id: I0d1383fbde82698bf6bdbbf275dadd7768bf0f8d
Reviewed-on: http://git.am.freescale.net:8181/10978
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Razvan Stefanescu <razvan.stefanescu@freescale.com>
Reviewed-by: Codrin Constantin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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This merges 3.12.15-rt25.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
drivers/misc/Makefile
drivers/net/ethernet/freescale/gianfar.c
drivers/net/ethernet/freescale/gianfar_ethtool.c
drivers/net/ethernet/freescale/gianfar_sysfs.c
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There are (probably rare) situations when a system crashed and the system
console becomes unresponsive but the network icmp layer still is alive.
Wouldn't it be wonderful, if we then could submit a sysreq command via ping?
This patch provides this facility. Please consult the updated documentation
Documentation/sysrq.txt for details.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
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Jon Masters developed this wonderful SMI detector. For details please
consult Documentation/hwlat_detector.txt. It could be ported to Linux
3.0 RT without any major change.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
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This patch provides a recording mechanism to store data of potential
sources of system latencies. The recordings separately determine the
latency caused by a delayed timer expiration, by a delayed wakeup of the
related user space program and by the sum of both. The histograms can be
enabled and reset individually. The data are accessible via the debug
filesystem. For details please consult Documentation/trace/histograms.txt.
Signed-off-by: Carsten Emde <C.Emde@osadl.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
drivers/mmc/card/block.c
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This reverts v3.13-rc3+ (78fd82238d0e5716) to v3.12, except for
commits which I noticed which appear relevant to the SDK.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Conflicts:
arch/powerpc/include/asm/kvm_host.h
arch/powerpc/kvm/book3s_hv_rmhandlers.S
arch/powerpc/kvm/book3s_interrupts.S
arch/powerpc/kvm/e500.c
arch/powerpc/kvm/e500mc.c
arch/powerpc/sysdev/fsl_soc.h
drivers/Kconfig
drivers/cpufreq/ppc-corenet-cpufreq.c
drivers/dma/fsldma.c
drivers/dma/s3c24xx-dma.c
drivers/misc/Makefile
drivers/mmc/host/sdhci-of-esdhc.c
drivers/mtd/devices/m25p80.c
drivers/net/ethernet/freescale/gianfar.h
drivers/platform/Kconfig
drivers/platform/Makefile
drivers/spi/spi-fsl-espi.c
include/crypto/algapi.h
include/linux/netdev_features.h
include/linux/skbuff.h
include/net/ip.h
net/core/ethtool.c
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Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
(cherry picked from commit 03aa254f1e3c3d902cd68763f8abc2387e82b4da)
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commit afc659241258b40b683998ec801d25d276529f43 upstream.
This patch adds the SMBus Device IDs for the Intel Wildcat Point-LP PCH.
Signed-off-by: James Ralston <james.d.ralston@intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
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So far the DIU driver does not have a mechanism to do the
board specific initialization. So on some platforms,
such as P1022, 8610 and 5121, The board specific initialization
is implmented in the platform file such p10222_ds.
Actually, the DIU is already intialized in the u-boot, the pin sharing
and the signal routing are also set in u-boot. So we can leverage that
in kernel driver to avoid board sepecific initialization, especially
for the corenet platform, which is the abstraction for serveral
platfroms.
The potential problem is that when the system wakeup from the deep
sleep, some platform settings may need to be re-initialized. The CPLD
and FPGA settings will be kept, but the pixel clock register which
usually locate at the global utility space need to be reinitialized.
Generally, the pixel clock setting was implemented in the platform
file, But the pixel clock register itself should be part of the DIU
module, And for P1022,8610 and T1040, the pixel clock register have the
same structure, So we can consider to move the pixel clock setting
from the platform to the diu driver. This patch provide the options
set the pixel clock in the diu driver. But the original platform pixel
clock setting stil can be used for P1022,8610 and 512x without any
update. To implement the pixel clock setting in the diu driver. the
following update in the diu dts node was needed.
display:display@180000 {
compatible = "fsl,t1040-diu", "fsl,diu";
- reg = <0x180000 1000>;
+ reg = <0x180000 1000 0xfc028 4>;
pixclk = <0 255 0>;
interrupts = <74 2 0 0>;
}
The 0xfc028 is the offset for pixel clock register. the 3 segment of
the pixclk stand for the PXCKDLYDIR, the max of PXCK and the
PXCKDLY which will be used by the pixel clock register setting.
This was tested on T1040 platform. For other platform, the original
node together with the platform settings still can work.
The binding update also included in this patch.
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Change-Id: I0663914b08378fc7852eab788801f4e5dc59977d
Reviewed-on: http://git.am.freescale.net:8181/10327
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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